1. Field of the Invention
The present invention relates to an information processing method for performing processing by using a CPU (Central Processing Unit) that comprises one and more register. More specifically, the present invention relates to a technique for enabling effective evacuation of the registers at the time of interruption.
2. Description of the Related Art
An interruption technique in the recent information processing method is used for various purposes in order to perform real-time response to the events such as a request from an input/output device and interval timer interruption.
As the basic interruption control performed in a CPU, there are a mode for accepting the interruption and a mode for not accepting the interruption. It is also possible to reject interruption (by each interruption) with the use of a masked bit that is set in advance on a state register, even if it is in the mode for accepting the interruption. Further, when the CPU selects either the mode for accepting the interruption or the mode for inhibiting the interruption, the control is carried out via writing in the state register. Therefore, when there is an interruption request during the execution of a certain process, an interruption is generated selectively on condition that the process is in a mode capable of accepting the interruption and an interruption request signal is not being masked. When an interruption is generated, the generated interruption is usually branched to proper interruption handlers. At this time, if the resources such as the register and the state register used in the user program are destroyed during the processing performed within the interruption handlers, it is not possible to restart the normal execution of the original user program after return from the interruption handlers. Therefore, when an interruption is generated, it is essential to evacuate the resources. However, practically, the entire resources containing the invalid resource are evacuated every time when accepting the interruption, since it is not possible to discriminate whether resources are valid or invalid.
A conventional technique disclosed in Japanese Published Patent Literature (Japanese Unexamined Patent Publication 2002-140199) provides a device to an instruction generating apparatus for judging whether the registers of the CPU are valid or not in order to selectively evacuate the contents of the valid register so as to reduce unnecessary evacuation of the register. Further, evacuation of the register is reduced through accepting the interruption only at the position where the number of valid registers is the least, so as to perform the interrupt processing at a much higher speed.
However, even in the case where only the valid registers are evacuated, it is not practically necessary to evacuate the register whose value does not change by the interrupt processing. Nonetheless, in the conventional technique, evacuation and return processing is carried out also on the register that is not necessary to be evacuated. As a result, it causes deterioration in the efficiency of the interrupt processing along with an increase in the memory capacity that is caused due to an increase in the amount of stack consumption.